Data-centric computing architectures that break the von Neumann memory bottleneck.
Hardware acceleration for large language models, optimizing inference and training efficiency.
Joint optimization of hardware and software for maximum AI workload performance.
FPGA-based adaptive architectures for flexible computing requirements.
Research focus on hardware-software co-design to accelerate large-scale AI computations and overcome memory bottlenecks in LLMs and data-intensive applications. Member of SAIL Research Group.
J. Gao, Z. Pu et al., "Smart Insole: Stand-Alone Soft 3-Axis Force Sensing Array in a Shoe," 2023 IEEE SENSORS, Vienna, Austria, 2023, pp. 1-4.
DOI: 10.1109/SENSORS56945.2023.10324863